1. Field of the Invention
This invention is related to a semiconductor memory device and in particular a semiconductor memory device arranged with a sense amplifier circuit for each memory string.
2. Description of the Related Art
In semiconductor memory devices such as NAND type flash memory, demand for semiconductor memory devices is increasing along with an increase in the uses of large volumes data. For example, in a NAND type flash memory, it is possible to store much more data with a reduction in chip size by a multi-bit technology in which two bits of data can be stored in one memory cell. In this type of semiconductor memory device, a plurality of memory strings with a plurality of memory cells connected in series, are arranged in parallel, a bit line BL is connected to each memory string, a word line WL is shared connection for each of a plurality of memory cells in a row direction and because access is possible in units of a page, data throughput is improved.
In order to further improve data throughput in the above stated semiconductor memory device, it is preferred that all the memory cells which are connected to one word line WL are read simultaneously. In this case, a sense amplifier circuit is connected to each bit line BL and it is necessary to prevent a decrease in bit line BL level detected by a sense amplifier circuit so that a pair of bit lines connected to adjacent memory strings are not affected by capacitive coupling.
In the above stated structure in which a sense amplifier circuit is connected to each bit line BL, a nonvolatile memory which is structured so that the detection operations of a sense amplifier circuit are not hindered while also preventing a decrease in bit line BL level is, for example, disclosed in Japan Laid Open Patent 2006-508483.
The above stated nonvolatile memory includes a structure in which a source line bias error is reduced which is generated by a current flowing to a finite resistance component which exists in a source line is reduced when the source line of a plurality of memory cells is grounded. This source line bias error makes a detection operation of a sense amplifier circuit incorrect. As a result, in the above stated nonvolatile memory, memory cells which have a conducting current higher than a boundary current value are identified and the generation of source line bias error is reduced by grounding the bit lines which are related to these identified memory cells.